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74F193 Up/Down Binary Counter with Separate Up/Down Clocks
April 1988 Revised July 1999
74F193 Up/Down Binary Counter with Separate Up/Down Clocks
General Description
The 74F193 is an up/down modulo-16 binary counter. Separate Count Up and Count Down Clocks are used, and in either counting mode the circuits operate synchronously. The outputs change state synchronously with the LOW-toHIGH transitions on the clock inputs. Separate Terminal Count Up and Terminal Count Down outputs are provided that are used as the clocks for subsequent stages without extra logic, thus simplifying multi-stage counter designs. Individual preset inputs allow the circuit to be used as a programmable counter. Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks.
Ordering Code:
Order Number 74F193SC 74F193SJ 74F193PC Package Number M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
(c) 1999 Fairchild Semiconductor Corporation
DS009497
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74F193
Unit Loading/Fan Out
U.L. Pin Names CPU CPD MR PL P0-P3 Q0-Q3 TCD TCU Description HIGH/LOW Count Up Clock Input (Active Rising Edge) Count Down Clock Input (Active Rising Edge) Asynchronous Master Reset Input (Active HIGH) Asynchronous Parallel Load Input (Active LOW) Parallel Data Inputs Flip-Flop Outputs Terminal Count Down (Borrow) Output (Active LOW) Terminal Count Up (Carry) Output (Active LOW) 1.0/3.0 1.0/3.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 50/33.3 50/33.3 Input IIH/IIL Output IOH/IOL 20 A/-1.8 mA 20 A/-1.8 mA 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA -1 mA/20 mA -1 mA/20 mA -1 mA/20 mA
Functional Description
The 74F193 is a 4-bit binary synchronous up/down (reversible) counter. It contains four edge-triggered flip-flops, with internal gating and steering logic to provide master reset, individual preset, count up and count down operations. A LOW-to-HIGH transition on the CP input to each flip-flop causes the output to change state. Synchronous switching, as opposed to ripple counting, is achieved by driving the steering gates of all stages from a common Count Up line and a common Count Down line, thereby causing all state changes to be initiated simultaneously. A LOW-to-HIGH transition on the Count Up input will advance the count by one; a similar transition on the Count Down input will decrease the count by one. While counting with one clock input, the other should be held HIGH, as indicated in the Function Table. The Terminal Count Up (TCU) and Terminal Count Down (TCD) outputs are normally HIGH. When the circuit has reached the maximum count state 15, the next HIGH-toLOW transition of the Count Up Clock will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again, thus effectively repeating the Count Up Clock, but delayed by two gate delays. Similarly, the TCD output will go LOW when the circuit is in the zero state and the Count Down Clock goes LOW. Since the TC outputs repeat the clock waveforms, they can be used as the clock input signals to the next higher order circuit in a multistage counter. TCU = Q0 * Q1 * Q2 * Q3 * CPU TCD = Q0* Q1 * Q2 * Q3 * CPD The 74F193 has an asynchronous parallel load capability permitting the counter to be preset. When the Parallel Load (PL) and the Master Reset (MR) inputs are LOW, information present on the Parallel Data input (P0-P3) is loaded into the counter and appears on the outputs regardless of the conditions of the clock inputs. A HIGH signal on the Master Reset input will disable the preset gates, override both clock inputs, and latch each Q output in the LOW state. If one of the clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted as a legitimate signal and will be counted.
Function Table
MR H L L L L PL X L H H H CPU X X CPD X X H Mode Reset (Asyn.) Preset (Asyn.) No Change Count Up Count Down
H
H
H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition
State Diagram
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74F193
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74F193
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) -0.5V to VCC -0.5V to +5.5V -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH IBVI ICEX VID IOD IIL IOS ICC Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current -60 38 4.75 3.75 -0.6 -1.8 Output Short-Circuit Current Power Supply Current -150 55 mA mA Max Max 10% VCC 5% VCC 10% VCC 2.5 2.7 0.5 5.0 100 7.0 50 A V A mA Max 0.0 0.0 Max VOUT = VCC IID = 1.9 A All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V (MR, PL, Pn) VIN = 0.5V (CPu, CPD) VOUT = 0V A Min 2.0 0.8 -1.2 Typ Max Units V V V V V Min Min Min Max Max VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -1 mA IOH = -1 mA IOL = 20 mA VIN = 2.7V VIN = 7.0V
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74F193
AC Electrical Characteristics
TA = +25C Symbol Parameter Min fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPLH tPHL tPLH tPHL tPLH tPHL Maximum Count Frequency Propagation Delay CPU or CPD to TCU or TCD Propagation Delay CPU or CPD to Qn Propagation Delay Pn to Qn Propagation Delay PL to Qn Propagation Delay MR to Qn Propagation Delay MR to TCU Propagation Delay MR to TCD Propagation Delay PL to TCU or TCD Propagation Delay Pn to TCU or TCD 7.0 7.0 7.0 6.5 12.0 11.5 11.5 11.0 15.5 14.5 14.5 14.0 7.0 7.0 7.0 6.5 16.5 15.5 15.5 15.0 ns 6.0 11.5 14.5 6.0 15.5 6.0 10.5 13.5 6.0 14.5 4.0 5.5 3.0 6.0 5.0 5.5 5.5 6.5 9.5 4.5 11.0 8.5 10.0 11.0 8.5 12.5 7.0 14.5 11.0 13.0 14.5 4.0 5.5 3.0 6.0 5.0 5.5 5.5 9.5 13.5 8.0 15.5 12.0 14.0 15.5 ns ns ns ns 100 4.0 3.5 VCC = +5.0V CL = 50 pF Typ 125 7.0 6.0 9.0 8.0 Max TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 90 4.0 3.5 10.0 9.0 ns Max MHz Units
ns
AC Operating Requirements
TA = +25C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tW(L) tW(L) tW(L) Setup Time, HIGH or LOW Pn to PL Hold Time, HIGH or LOW Pn to PL PL Pulse Width, LOW CPU or CPD Pulse Width, LOW CPU or CPD Pulse Width, LOW (Change of Direction) tW(H) tREC tREC MR Pulse Width, HIGH Recovery Time PL to CPU or CPD Recovery Time MR to CPU or CPD 4.0 4.0 ns 6.0 6.0 6.0 6.0 ns ns 10.0 10.0 ns 4.5 4.5 2.0 2.0 6.0 5.0 Max TA = 0C to +70C VCC = +5.0V Min 5.0 5.0 2.0 2.0 6.0 5.0 ns ns ns Max Units
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74F193
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D
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74F193 Up/Down Binary Counter with Separate Up/Down Clocks
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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